Latch-up is a condition where a low impedance path is created between supply and ground.
This condition is caused by a trigger (current injection or overvoltage), but once activated,
the low impedance path remains even after the trigger is no longer present.
This behavior may cause circuit malfunctions resulting in the destruction of the whole device due to high current.
The latch-up condition typically requires a power cycle to eliminate the low impedance path.
Power cycling is the act of turning a piece of equipment off and then on again.
CMOS circuits use NMOS and PMOS transistors to create the circuit functions.
In the design of the CMOS integrated circuit, the proximity of the PN junctions that form
the NMOS and PMOS transistors create inherent parasitic transistors and diodes.
These parasitic structures create PNPN Thyristors, build up by npn- and pnp-bipolar junction transistors.
Excursions outside the normal operating voltage and current levels can trigger PNPN Thyristors and may cause latch-up.
Also the product of the gains of the two parasitic transistors in the feedback loop, $\beta_1\times\beta_2$,
has to be greater than one to make latch-up possible.
Picture 1: CMOS structure with latch-up parasitics in cross section view
Latch-up may begin when sufficient current flows through $R_p$ to turn on the npn-transistor $(I*Rp > 0.7 \,\text{V})$
due to a noise spike or an improper circuit hookup, this will push current through $R_n$.
If the voltage drop across $R_n$ is high enough, the pnp-transistor will also turn on,
and a self-sustaining low resistance path between the power rails is formed.
Picture 2: equivalent circuit for latch-up parasitics
Preventing latch-up
There are some actions which can be taken to reduce the possible onset of latch-up:
Reduce the gain product $\beta_1\times\beta_2$:
Larger spacing of source/drain areas to the well-borders will increase the base width and worsens the parasitic transistor.
Buried n+ layer in well reduces gain $\beta$ of the pnp-transistor.
Reduce the resistances, producing lower voltage drops:
Guard rings around p- and n-well, with frequent contacts to the rings: Guard rings act as injected carrier syphons allowing these carriers to flow to the supply or ground.
The use of substrate ties and well taps act as excited carrier syphons.
Use an EPI (epitaxial silicon) layer. The EPI layer is more lightly doped than the substrate that is highly doped.
The heavily doped layer acts as a current sink where excess minority carriers can quickly recombine.
Make low resistance connections to GND and supply.
Picture 3: Layout view of p-MOSFETs and n-MOSFETs surrounded by guard rings
Isolation to avoid parasitics:
Technologies which uses deep trenches to separate device groups avoid or weakens the parasitics.
Picture 4: Cross section of MOSFETs separated by deep trench isolation
Deep trenches combined with silicon-on-insulator technologies are inherently latch-up-resistant due to total isolation and no latch-up-parasitics.
Picture 5: Cross section of MOSFETs separated by deep trench isolation and silicon-on-insulator
Avoid to overcome maximum ratings, use protections and careful handling:
Use a Latch-up Protection Technology (LPT) circuit. When a latch-up is detected, the LPT circuit shuts down the chip and holds it powered-down for a preset time.
Make sure power supplies are off before plugging a board. A "hot plug in" of an unpowered circuit
may cause signal pins to see voltages greater than 0.7 V higher than $V_{dd}$.
When the chip comes up to full power, sections of it could be latched.
Carefully protect electrostatic protection devices associated with I/O pads with guard rings.
ESD enters the circuit through an I/O pad, where it is clamped to one of the rails by the ESD protection circuit.
Devices in the protection circuit can inject minority carriers in the substrate or well, potentially triggering latchup.
Sudden transients on the power or ground bus, which may occur if large numbers of transistors switch simultaneously, can drive the circuit into latchup.
Whether this is possible should be checked through simulation.
Radiation, including x-rays, cosmic, or alpha rays, can generate electron-hole pairs as they penetrate the chip.
These carriers can contribute to well or substrate currents.
