Latch-up is a condition where a low impedance path is created between supply and ground. This condition is caused by a trigger (current injection or overvoltage), but once activated, the low impedance path remains even after the trigger is no longer present. This behavior may cause circuit malfunctions resulting in the destruction of the whole device due to high current. The latch-up condition typically requires a power cycle to eliminate the low impedance path. Power cycling is the act of turning a piece of equipment off and then on again.

CMOS circuits use NMOS and PMOS transistors to create the circuit functions. In the design of the CMOS integrated circuit, the proximity of the PN junctions that form the NMOS and PMOS transistors create inherent parasitic transistors and diodes. These parasitic structures create PNPN Thyristors, build up by npn- and pnp-bipolar junction transistors. Excursions outside the normal operating voltage and current levels can trigger PNPN Thyristors and may cause latch-up. Also the product of the gains of the two parasitic transistors in the feedback loop, $\beta_1\times\beta_2$, has to be greater than one to make latch-up possible.

latch-up_cross section
Picture 1: CMOS structure with latch-up parasitics in cross section view

Latch-up may begin when sufficient current flows through $R_p$ to turn on the npn-transistor $(I*Rp > 0.7 \,\text{V})$ due to a noise spike or an improper circuit hookup, this will push current through $R_n$. If the voltage drop across $R_n$ is high enough, the pnp-transistor will also turn on, and a self-sustaining low resistance path between the power rails is formed.

Picture 2: equivalent circuit for latch-up parasitics

Preventing latch-up

There are some actions which can be taken to reduce the possible onset of latch-up:

  1. Reduce the gain product $\beta_1\times\beta_2$:
  2. Reduce the resistances, producing lower voltage drops:
  3. guard ring_layout
    Picture 3: Layout view of p-MOSFETs and n-MOSFETs surrounded by guard rings
  4. Isolation to avoid parasitics:
  5. Avoid to overcome maximum ratings, use protections and careful handling:


state of all references: 12.07.2016
made by Michael Pinter, 12.07.2016